1. Field of the Invention
The present invention relates to an organic light emitting display device driving apparatus and a driving method thereof, and more particularly to an organic light emitting diode (OLED) display device driving apparatus and a driving method thereof for reducing the power consumption of the driving apparatus and increasing the driving speed by making a scan driving circuit in the passive matrix typed OLED display driving apparatus have 3-state output. (Herein after, it will be referred to as OLED panel driving apparatus.)
2. Background of the Related Art
A liquid crystal display device is widely used as an image display device of one of TV, a computer, or a portable phone, but it has disadvantages of being thick, heavy, and slow response speed since it requires a back light installed therein. An organic light emitting diode (OLED) display panel is recognized as an image display device which can replace such a display as above (Herein after, it will be referred to as ‘OLED panel’.). The OLED panel includes a very thin organic film being 0.1 μm or being less than 0.1 μm in thickness. When electric current is applied to the organic thin film, electrons and holes are recoupled near the interface of an electron transport layer and a hole transport layer so as to emit light. The light-emitting shows very fast response time less than hundreds of nano seconds. As such, OLED is composed of two polar structure groups, and it is driven by an electric current due to the difference of voltage-current characteristics of a discrete OLED to form a panel.
FIG. 1 is a schematic block diagram of a conventional free charge type of an OLED panel driving apparatus. As shown in FIG. 1, an OLED panel 10 includes a plurality of common anode lines D1, . . . , Dm) and a plurality of common cathode lines S1, . . . , Sn, which intersect in a matrix shape, and an OLED 12 is placed at each intersecting point of the matrix, to form a pixel (one pixel being composed of R/G/B.) A data driving circuit 20 is connected to the common anode lines D1, . . . , Dm, and a scan driving circuit 30 is connected to the common cathode lines S1, . . . , Sn.
A scan driving circuit 30 includes a scan output unit 32 which selectively connects the common cathode lines S1, . . . , Sn to a high voltage terminal VH (for example, 15 V) and a grounding earth by a predetermined pattern in accordance with the control of a controlling unit (not shown). FIG. 2 is a detailed circuit diagram of a scan output unit with respect to one of the common cathode lines of FIG. 1. As shown in FIG. 2, the scan output unit 32 selectively connects one common cathode line Sy to a high voltage terminal VH or a grounding earth GND in accordance with the logic level of a control signal CSCAN from an outer controlling unit (not shown).
FIG. 3 is a detailed circuit diagram of a data output unit with respect to one common anode line of FIG. 1. As shown in FIG. 3, the data output unit 22 selectively connects each of the common anode lines D1, . . . , Dm to a constant current source CC or a grounding earth GND in accordance with the control of a controlling unit (not shown).
In the structure described as above, if the scan output unit 32 turns “on” or “off” alternately so as to select any one of the common cathode lines from a first row S1 to an nth row Sn, the data output unit 22 connects the common anode lines D1, . . . , Dm to the constant current source CC for the time width varied by Pulse Width Modulation (PWM) method in accordance with the gray scale of a corresponding pixel, that is, the OLED 12 with synchronized thereto, and a current is applied to the corresponding OLED 12 so as to form one display frame.
In the meantime, a parasitic capacitor C exists on the both ends of the anode and the cathode of a diode D since the OLED 12 is composed of an organic thin film, which causes a problem of not-treating of low gray scale in the presence of the parasitic capacitor C. Thus, conventionally, a voltage is applied just as much as to turn “on” the diode D before PWM current is applied on the common anode lines D1, . . . , Dm so that the parasitic capacitor C is precharged. Then, for the purpose, a predetermined voltage, for example, precharge voltage terminal VPRE of about 4˜6 V is further provided on the data output unit 22.
FIG. 4 is a timing chart to illustrate the relations of a scan output timing for one image frame in the conventional precharge-typed OLED panel driving apparatus, and a precharge interval and a data output interval in each scan output interval. As shown in FIG. 4, the vertical synchronization signal Vsync is generated every one frame of display, and horizontal synchronization signals Hsync is generated having the same number as that of the common cathode lines n, in the vertical scan period between the vertical synchronization signal Vsync, and data is applied to the all common anode lines D1, . . . , Dm in the horizontal scan period between the horizontal synchronization signal Hsync at the same time. That is, if the scan output unit 32 connects a first row of common cathode line S1 to the grounding earth GND in the high voltage terminal VH in accordance with the outer control signal CSCAN generated with synchronized to the down edge of each horizontal synchronization signal Hsync, the data output unit 22 connects the all common anode lines D1, . . . , Dm into a precharge voltage VPRE in accordance with the control of the outer control signal with synchronized thereto for a predetermined time so as to charge the parasitic capacitor C of the OLED 12. Then, the data output unit 22 connects each of the common anode lines D1, . . . , Dm to the constant current source CC in accordance with the control of the outer control signal PWM, for the PWM time predetermined according to the pixel gray of the OLED 12 connected thereto so that the OLED 12 emits light. Then, if the data output unit 22 again connects the common anode lines D1, . . . , Dm to the grounding earth GND in accordance with the control of the outer control signal Reset, the voltage charged in the parasitic capacitor C is discharged. In the same way, the process is executed for up to the nth row of the common cathode line Sn, so as to form a display one frame.
However, according to the OLED panel driving apparatus of the conventional precharge typed OLED panel driving apparatus described as above, since the all parasitic capacitors C, connected thereto in parallel, are repeatedly charged and discharged (eventually, because of the conversion of the voltage polarity of the both ends of the OLED), in the process in which the data output unit 22 operates the common anode lines D1, . . . , Dm, large amount of current is flowed in the OLED panel 10, and the power consumption according thereto is as follows by Equation 1.Pd=n*m*C*VH2*fclk  [Equation 1]
In the Equation 1, the number from 1 to n presents the number of the common cathode lines, m presents the number of the common anode lines, C presents a parasitic capacitance, VH presents high voltage applied to the anode, and fclk presents the operation frequency of the scan driving circuit 30. As shown in Equation 1, since the conventional OLED panel driving apparatus requires a large amount of current during charge-discharge, the power consumption is increased, and the operation speed of the data driving circuit is decreased.